The invention is in the field of Read Only Memory (ROM) devices, and relates specifically to Electrically Erasable and Programmable Read Only Memory (EEPROM) devices.
EEPROM devices in general, and methods for making such devices, are well known in the art. Typically, an EEPROM structure has a floating gate and a control gate, both of which are typically fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive. A typical doping material is phosphorus.
The floating gate is separated from a substrate region by a gate dielectric layer of insulating material such as silicon dioxide, while the substrate region includes source and drain regions with a channel region therebetween. The floating gate and the control gate are separated by an intergate dielectric, typically silicon dioxide. The basic principle upon which EEPROM devices operate is that charge is stored on the floating gate in a capacitive manner and can subsequently be electrically erased.
The typical write or erase voltage, i.e. the voltage which is needed to place charge on or to remove charge from the floating gate, has typically been high, i.e. in excess of 20 volts. In turn, this places shrinkage limits on gate oxide thickness of control transistors, junction depth and die size.
Silicon nitride (Si.sub.3 N.sub.4) has also been used in an insulating layer of a dual dielectric (thermal oxide with silicon nitride on it) between the floating gate and the control gate. Silicon nitride has the property that it is more dense than silicon dioxide, and, therefore, affords higher capacitive coupling between the floating gate and the control gate. A typical dual dielectric between the floating gate and the control gate is composed of 500 angstroms or less oxide and 400 angstroms or less nitride. However, even with the use of silicon nitride as the insulating layer, the write and erase voltage is still relatively high, typically in excess of 18 volts. High erase and program voltages for conventional EEPROM devices are a major drawback. Use of such high voltages has required a separate high voltage supply when operating the devices, or the use of special voltage multiplying circuitry within the device to boost the supply voltage to the requisite program and erase levels.
An additional drawback is that earlier EEPROM structures, when used in a memory array, require additional control circuitry to isolate individual storage cells from one another. This increases the device geometry. For example, given the requirement of a control transistor for each EEPROM cell, the equivalent space requirement for early EEPROM cells was about 165 square microns. More recent designs reduced this figure to below 100 square microns, but substantial further reductions were still required.
In order to overcome these disadvantages, a compact EEPROM device using only a single lateral transistor is shown in Mukherjee et al U.S. Pat. No. 4,698,787, incorporated herein by reference. The EEPROM device described in that patent achieves a smaller surface area than earlier EEPROM devices, while at the same time requiring substantially lower programming and erasing voltages. Nevertheless, as integration techniques have advanced, integrated circuit chip densities have continued to grow, and the need has arisen for a still more compact memory cell configuration, as well as for a memory cell which is capable of operating with still lower programming and erasing voltages.
One technique which has been employed to further shrink memory cell size is the provision of the floating gate and the control gate within a trench, so that a portion of the cell geometry is provided in the vertical direction, thus reducing the lateral extent of the memory cell. In U.S. Pat. No. 4,796,228, there is shown a multiple-transistor EEPROM memory cell in which a lateral transistor employs a trench configuration between laterally-disposed source and drain regions, with electron tunneling at the upper surface of the device between doped surface regions and upper corners of the trench. This cell still has several disadvantages, however, including the need for a relatively large area to accommodate the multi-transistor cell configuration, as well as the extra space required because of the lateral configuration of the individual transistors of the memory cell and the need for relatively high programming and erase voltages.
Various trench configurations have also been employed in other types of memory devices, such as Electrically Programmable Read Only Memory (EPROM) devices and the like, as shown, for example, in Japanese Kokai Numbers 1-227477, 61-256673, 62-76563, and 63-36561. However, none of these nonvolatile memory applications with vertical constructions offer efficient means for both electrical programming and electrical erasing, and are thus of limited utility in EEPROM devices.